//vga ctl module of vga_test
//Author:Liuhao
//Date:04,04.2018

/********************************************************************/
//module & IO declaratioi
module	vga_basemod(
	sys_rst_n,
	sys_clk,
	vga_en,

	vga,
	vga_H,
	vga_V
);

input	sys_rst_n;
input	sys_clk;
input	vga_en;

output [15:0] vga;
output vga_H;
output vga_V;

/***********************************************************/
`define vga_1920x1080
//`define vga_1280x1024
//`define vga_1280x960
//`define vga_1024x768
//`define vga_800x600
//`define vga_640x480

/***********************************************************/
`ifdef vga_1920x1080
	parameter H_sync_bit = 12;
	parameter H_front_bit = 28;
	parameter H_dis_bit = 1920;
	parameter H_back_bit = 40;
	parameter H_bit = 2000;
	
	parameter V_sync_bit = 4;
	parameter V_front_bit = 3;
	parameter V_dis_bit = 1080;
	parameter V_back_bit = 18;
	parameter V_bit = 1105;
`endif

/***********************************************************/
//module enable control
wire vga_clk;
reg vga_en_r;

always @ (posedge sys_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		vga_en_r <= 1'b0;
	else
		vga_en_r <= vga_en;
end

assign vga_clk = sys_clk && vga_en_r;

/***********************************************************/
//H & V counter
reg [12:0] Hcnt;
reg [12:0] Vcnt;

always @ (posedge vga_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		Hcnt <= 13'b0;
	else if(Hcnt >= H_bit)
		Hcnt <= 13'b0;
	else
		Hcnt <= Hcnt + 13'b1;
end

always @ (posedge vga_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		Vcnt <= 13'b0;
	else if(Hcnt == H_bit)
		begin
			if(Vcnt >= V_bit)
				Vcnt <= 13'b0;
			else
				Vcnt <= Vcnt + 13'b1;
		end
	else
		;
end

/***********************************************************/
//H & V output control
reg vga_H_r;
reg vga_V_r;

always @ (posedge vga_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		vga_H_r <= 1'b0;
	else if(Hcnt == H_sync_bit)
		vga_H_r <= 1'b1;
	else if(Hcnt == H_bit)
		vga_H_r <= 1'b0;
	else
		;
end

always @ (posedge vga_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		vga_V_r <= 1'b0;
	else if(Vcnt == V_sync_bit)
		vga_V_r <= 1'b1;
	else if(Vcnt == V_bit)
		vga_V_r <= 1'b0;
	else
		;
end

assign vga_V = vga_V_r;
assign vga_H = vga_H_r;

/***********************************************************/
//pixel output control
reg [15:0] vga_r;

always @ (posedge vga_clk or negedge sys_rst_n)
begin
	if(!sys_rst_n)
		vga_r <= 16'b0;
	else if((Vcnt >= 8) && (Vcnt <= 1087))
		begin
			if((Hcnt >= 41) && (Hcnt <= 681))
				vga_r <= 16'b11111_000000_00000;
			else if((Hcnt >= 682) && (Hcnt <= 1321))
				vga_r <= 16'b00000_111111_00000;
			else if((Hcnt >= 1322) && (Hcnt <= 1960))
				vga_r <= 16'b00000_000000_11111;
			else
				;
		end
	else
		vga_r <= 16'b0;
end

assign vga = vga_r;

/************************************************************/

endmodule
/********************************************************************/

